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KM29V040T, km29v040it flash memory 1 document title 512k x 8 bit nand flash memory revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. revision no. 0.0 1.0 1.1 remark final history data sheet 1997. data sheet 1998. data sheet 1998. draft date april 10th 1997 april 10th 1998 july 14th 1998
KM29V040T, km29v040it flash memory 2 512k x 8 bit nand flash memory the km29v040 is a 512kx8bit nand flash memory. its nand cell structure provides the most cost-effective solution for digi- tal audio recording. a program operation programs a 32-byte frame in typically 500 m s and an erase operation erase a 4k- byte block in typically 6ms. data in a frame can be read out at a burst cycle rate of 120ns/byte. the i/o pins serve as the ports for address and data input/output as well as for command inputs. the on-chip write controller automates the program and erase operations, including program or erase pulse repetition where required, and performs internal verification of cell data. the km29v040 is an optimum solution for flash memory appli- cation that do not require the high performance levels or capac- ity of larger density flash memories. these application include data storage in digital telephone answering devices(tad) and other consumer applications that require voice data storage. general description features single 3.3 - volt power supply organization - memory cell array : 512k x 8 - data register : 32 x 8 bit automatic program and erase (typical) - frame program : 32 byte in 500 m s - block erase : 4k byte in 6ms 32-byte frame read operation - random access : 15 m s(max.) - serial frame access : 120ns(min.) command/address/data multiplexed i/o port low operation current (typical) - 10 m a standby current - 10ma read/ program/erase current reliable cmos floating-gate technology - endurance : 100k program/erase cycles 44(40) - lead tsop type ii (400mil / 0.8 mm pitch) pin configuration vss cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o0 i/o1 i/o2 i/o3 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 vcc i/o4 i/o5 i/o6 i/o7 n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c gnd r/ b re ce vcc 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44(40) tsop (ii) note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc, v ss or gnd inputs disconnected. pin description pin name pin function i/o 0 ~ i/o 7 data inputs/outputs cle command latch enable ale address latch enable ce chip enable re read enable we write enable wp write protect gnd ground input r/ b ready/busy output v cc power v ss ground n.c no connection
KM29V040T, km29v040it flash memory 3 figure 1. functional block diagram figure 2. array organization note : * (1) : x can be v il or v ih i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 3rd cycle a 16 a 17 a 18 x* (1) x* x* *x *x column address (a 0 -a 4 ) frame address (a 5 -a 6 ) row address (a 7 -a 11 ) block address (a 12 -a 18 ) 128byte column 4m : 4k row (=128 blocks) 32 byte 8 bit good block i/o 0 ~ i/o 7 1 frame = 32 byte 1 row = 4 frames = 128 bytes 1 block = 32 rows = 4k bytes 1 device = 32b x 4frames x 32rows x 128blocks = 4mbits frame register 1 2 3 4 x-buffers 4m bit command nand flash array 32byte x 4frame x 4096row y-gating page register & s/a i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers a 7 - a 18 a 0 - a 6 command ce re we cle ale wp i/o 0 i/o 7 the 1st block (4kb) 1block(32row) (4k byte)
KM29V040T, km29v040it flash memory 4 product introduction the km29v040 is a 4m bit memory organized as 4096 rows by 1024 columns. a 256-bit data register is connected to memory cell arrays accommodating data transfer between the registers and the cell array during frame read and frame program operations. the memory array is composed of unit nand structures in which 8 cells are connected serially. each of the 8 cells reside in a different row. a block consists of the 32 rows, totaling 4096 unit nand structures of 8bits each . the array organization is shown in figure 2. the program and read operations are executed on a frame basis, while the erase operatio n is executed on a block basis. the memory array consists of 128 separately erasable 4k-byte blocks. the km29v040 has addresses multiplexed into 8 i/o pins. this scheme not only reduces pin count but allows systems upgrades to higher density flash memories by maintaining consistency in system board design. command, address and data are all written through i/o s by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. all commands require one bus cycle except for block erase command which requires two cycles. for byte-level addressing, the 512k byte physical space requires a 19-bit address, low row address and high row address. frame read and frame program require the same three address cycles following by a command input. in the block erase operation, however, only the two row address cycles are required. device operations are selected by writing specific commands into the command register. table 1 defines the specific commands of the km29v040. table 1. command sets function 1st. cycle 2nd. cycle acceptable command during busy read 00h - reset ffh - o frame program 80h 10h block erase 60h d0h status read 70h - o read id 90h -
KM29V040T, km29v040it flash memory 5 pin description command latch enable(cle) the cle input controls the path activation for commands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. address latch enable(ale) the ale input controls the path activation for address and input data to the internal address/data register. addresses are latch ed on the rising edge of we with ale high, and input data is latched when ale is low. chip enable( ce ) the ce input is the device selection control. when ce goes high during a read operation the device is returned to standby mode. however, when the device is in the busy state during program or erase, ce high is ignored, and does not return the device to standby mode. write enable( we ) the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. read enable( re ) the re input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid t rea after the falling edge of re which also increments the internal column address counter by one. i/o port : i/o 0 ~ i/o 7 the i/o pins are used to input command, address and data, and to output data during read operations. the i/o pins float to high- z when the chip is deselected or when the outputs are disabled. write protect( wp ) the wp pin provides inadvertent write/erase protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. ready/ busy (r/ b ) the r/ b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
KM29V040T, km29v040it flash memory 6 dc and operating characteristics (recommended operating conditions otherwise noted.) parameter symbol test conditions min typ max unit operating current burst read cycle i cc1 tcycle=120ns ce =v il , i out =0ma - 5 10 ma command, address input i cc3 tcycle=120ns - 5 10 ma data input i cc4 tcycle=120ns - 5 10 ma program i cc5 - - 5 10 ma erase i cc6 - - 5 10 ma stand-by current(ttl) i sb1 ce =v ih , wp =0v/v cc - - 1 ma stand-by current(cmos) i sb2 ce =v cc -0.2, wp =0v/v cc - 10 50 m a input leakage current i li v in =0 to 3.6v - - 10 m a output leakage current i lo v out =0 to 3.6v - - 10 m a input high voltage, all inputs v ih - 2.4 - v cc +0.3 v input low voltage, all inputs v il - -0.3 - 0.6 v output high voltage level v oh i oh =-400 m a 2.4 - - v output low voltage level v ol i ol =2.1ma - - 0.4 v output low current(r/ b ) i ol (r/ b ) v ol =0.4v 8 10 - ma absolute maximum ratings note : 1. minimum dc voltage is -0.3v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input/output pins is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating con ditions for extended periods may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v in -0.6 to +5.5 v temperature under bias KM29V040T t bias -10 to +125 c km29v040it -40 to +125 storage temperature t stg -65 to +150 c short circuit output current i os 5 ma recommended operating conditions (voltage reference to gnd, KM29V040T : t a =0 to 70 c, km29v040it : t a =-45 to 85 c) parameter symbol min typ. max unit supply voltage v cc 3.0 3.3 3.6 v supply voltage v ss 0 0 0 v
KM29V040T, km29v040it flash memory 7 capacitance ( t a =25 c, v cc =3.3v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input / output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf valid block note : 1. the km29v040 may or may not include bad blocks. bad blocks are defined as blocks that contain one or more bad bits. do not tr y to access these bad blocks for program and erase. the minimum valid blocks are guaranteed for 10years data retention or 1m program erase cycling . (refer to the attached technical notes ) 2. the 1st block, which is placed on 00h block address, is guaranteed to be a good block. parameter symbol min typ. max unit valid block number n vb 125 - 128 block program/erase characteristics parameter symbol min typ max unit program time t prog - 0.5 1 ms number of partial program cycles in the same frame nop - - 10 cycles block erase time t bers - 6 10 ms mode selection note : 1. x can be v il or v ih 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode h l l h x read mode command input l h l h x address input(3clock) h l l h h write mode command input l h l h h address input(3clock) l l l h h data input l l l h x sequential read & data output l l l h h x during read(busy) x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect x x h x x 0v/v cc (2) stand-by ac test condition (KM29V040T:t a =0 to 70 c, km29v040it:t a =-40 to 85 c, v cc =3.3v 10% unless otherwise noted) parameter value input pulse levels 0.4v to 2.6v input rise and fall times 5ns input and output timing levels 0.8v and 2.0v output load 1 ttl gate and cl=100pf
KM29V040T, km29v040it flash memory 8 ac characteristics for operation note : 1. if ce goes high within 50ns after the third address input, r/ b will not return to v ol . 2. the time to ready depends on the value of the pull-up resistor tied r/ b pin. parameter symbol min max unit data transfer from cell to register t r - 15 m s ale to re delay t ar 250 - ns ce low to re low (id read) t cr 250 - ns ready to re low t rr 100 - ns re pulse width t rp 60 - ns we high to busy t wb - 200 ns read cycle time t rc 120 - ns re access time t rea - 50 ns re high to output hi-z t rhz 0 30 ns ce high to output hi-z t chz - 50 ns re high hold time t reh 40 - ns output hi-z to re low t ir 0 - ns ce high to ready(in case of interception by ce at read) (1) t cry - 100+tr(r/ b ) (2) ns re low to status output t rsto - 60 ns ce low to status output t csto - 70 ns we high to re low t whr 50 - ns re access time(read id) t whrid 100 - ns device resetting time (read/program/erase) t rst - 5/10/500 m s ac timing characteristics for command / address / data input parameter symbol min max unit cle set-up time t cls 50 - ns cle hold time t clh 50 - ns ce setup time t cs 50 - ns ce hold time t ch 50 - ns we pulse width t wp 60 - ns ale setup time t als 50 - ns ale hold time t alh 50 - ns data set-up time t ds 40 - ns data hold time t dh 20 - ns write cycle time t wc 120 - ns we high hold time t wh 40 - ns
KM29V040T, km29v040it flash memory 9 identifying invalid block(s) in the km29v040 invalid blocks the km29v040 flash device may or may not contain up to 3 invalid blocks. invalid blocks are defined as blocks that contain one o r more invalid bits. typically, an invalid block will contain a single bad bit. devices with invalid block(s) have the same qualit y levels as devices with all valid blocks and have the same ac and dc characteristics. an invalid block(s) does not affect the performance o f valid block(s) because it is isolated from the bit line and the common source line by a select transistor. the system design mus t be able to mask out the invalid block(s) via address mapping. the 1st block of the km29v040, however, is fully guaranteed to be a g ood block. km29v040 technical notes all device locations are erased(ffh) prior to shipping. device with invalid block(s) will be randomly written with 00h data with in the first or second page in the invalid block(s). this page may or may not contain the invalid cell(s). the 00h data just marks the block(s) that contains the invalid cell(s). a system that can utilize these devices must be able to recognize invalid block(s) via the fo llowing suggested flow chart (figure 1). figure 1. flow chart to create invalid block table. start set : block = 0 check "ff" ? set : block n + 1 block = 127 ? end create (or update) invalid block(s) table no no yes yes * for the 1st frame of 1st page *
KM29V040T, km29v040it flash memory 10 error in program or erase operation the device may fail during a program or erase operation. the following possible failure modes should be considered when implementing a highly reliable system. km29v040 technical notes (continued) failure mode detection and countermeasure sequence block erase failure read after erase --> block replacement frame program failure status read after program --> block replacement single bit program failure ("1" --> "0") block verify after program --> retry or ecc ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection block replacement when the error happens in block "a", try to reprogram the data into another block "b" by reloading from an external buffer. then, prevent further system access to block "a"(by creating a "bad block" table or other appropriate scheme.) during program operation ; during erase operation ; when the error occurs after an erase operation, prevent future accesses to this bad block (again by creating a table within the system or other appropriate scheme.) buffer memory error occurs block a block b
KM29V040T, km29v040it flash memory 11 * command latch cycle ce we cle ale i/o 0 ~ 7 command * address latch cycle ce we cle ale i/o 0 ~ 7 a 0 ~a 7 a 8 ~a 15 a 16 ~a 18 t cls t cs t clh t ch t wp t als t alh t ds t dh t cls t cs t wc t wc t wp t wp t wh t wh t als t alh t ds t dh t ds t dh t ds t dh t wp
KM29V040T, km29v040it flash memory 12 * input data latch cycle ce cle we i/o 0 ~ 7 din 0 din 1 din 31 ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp * burst read cycle after frame access (cle=l, we =h, ale=l) re ce r/ b i/o 0 ~ 7 dout dout dout t rc t rp t rea t rr t rhz* t rea t reh t rea t rhz* t rhz ? ? ?
KM29V040T, km29v040it flash memory 13 * status read cycle ce we cle re i/o 0 ~ 7 notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 70h status output t cls t clh t rea t wp t ch t ds t dh t rsto t ir t rhz* t chz* t whr t csto read operation (read one frame) ce cle r/ b i/o 0 ~ 7 we ale re busy dout n dout n+1 dout n+2 dout n+3 dout 32 column address row address t wb t ar t r t chz t rc t rhz t rr 00h a 0 ~ a 7 a 8 ~ a 15 a 16 ~ a 18 ? ? ?
KM29V040T, km29v040it flash memory 14 read operation (intercepted by ce ) ce cle r/ b i/o 0 ~ 7 we ale re busy dout n dout n+1 dout n+2 dout n+3 row address t wb t ar t chz t r t rr address column 00h a 0 ~a 7 a 8 ~a 15 a 16 ~a 18 ce cle r/ b i/o 0 ~ 7 we ale re program operation 80h 70h i/o 0 din n din din 10h 31 n+1 a 0 ~ a 7 a 16 ~ a 18 a 8 ~ a 15 sequential data input command column address row address 1 up to 32 byte data serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t wc t wc t wc t wb t prog ? ? ? ? ?
KM29V040T, km29v040it flash memory 15 ce cle r/ b i/o 0 ~ 7 we ale re block erase operation 60h a 16 ~a 18 a 8 ~a 15 auto block erase setup command erase command doh busy t wb t bers block address ?
KM29V040T, km29v040it flash memory 16 device operation frame read upon initial device power up or after excution of reset(ffh) command, the device defaults to read mode. this operation is also i ni- tiated by writing 00h to the command register along with three address cycles. the three cycle address input must be given for access to each new frame. the read mode is enabled when the frame address is changed. 32 bytes of data within the selected frame are transferred to the d ata registers in less than 15 m s(t r ). the cpu can detect the completion of this data transfer(t r ) by analyzing the output of r/ b pin. once the data in a frame is loaded into the registers, they may be read out in 120ns cycle time by sequentially pulsing re with ce staying low. high to low transitions of the re clock output the data starting from the selected column address up to the last column address within the frame(column 32). figure 3. read operation start add.(3cycle) 00h busy(seek time) a 0 ~a 7 & a 8 ~a 18 data output(sequential) seek time 0 31 ce cle ale re we i/o 0 ~ 7 r/ b
KM29V040T, km29v040it flash memory 17 frame program the device is programmed on a frame basis. the addressing may be done in random order in a block. a frame program cycle consist of a serial data loading period in which up to 32 bytes of data must be loaded into the device, and a nonvolatile programming p eriod in which the loaded data is programmed into the appropriate cells. the sequential data loading period begins by inputting the frame program setup command(80h), followed by the three cycle address input and then sequential data loading. the bytes other than those to be programmed do not need to be loaded. the frame program confirm command(10h) initiates the programming process. writing 10h alone without previously entering the serial data will not initiate the programming process. the internal write controller automatically executes the algorithms and t imings necessary for program and verify, thereby freeing the cpu for other tasks. the cpu can detect the completion of a program cycle by monitoring the r/ b output, or the status bit(i/o 6 ) of the status register. only the read status command and reset command are valid while programming is in progress. when the frame program is complete, the write status bit(i/o 0 ) may be checked. the inter- nal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains in read sta- tus command mode until another valid command is written to the command register. figure 4. frame program operation 80h a 0 ~a 7 & a 8 ~a 18 i/o 0 ~ 7 r/ b address & data input 32 byte data 10h frame program while the frame size of the device is 32 bytes, not all the bytes in a frame have to be programmed at once. the device supports par- tial frame programming in which a frame may be partially programmed up to 10 separate program operations. the program size in each of the 10 partial program operations is freely determined by the user and do not have to be equal to each other or to any p reset size. however, the user should ensure that the partial program units within a frame do not overlap as "0" data cannot be changed to "1" data without an erase operation. to perform a partial frame program operation, the user only writes the partial frame data t hat is to programmed. just as in the standard frame program operation, an 80h command is followed by start address data. however, only the partial program data need be divided when programming a frame in 10 partial program operations. figure 5. example of dividing a frame into 10 partial program units fa a2 43 cb 81 28 e0 2a d5 - - - - - - 32 b5 7d 6f aa e1 d7 c0 single frame 1st partial program start address (00h) 2nd partial program start address (04h) 3rd partial program start address (06h) : : : : : : 9th partial program start address (18h) 10th partial program start address (1fh) 10th partial frame program data 9th partial frame program data 3rd partial frame program data : : : : : : 2nd partial frame program data 1st partial frame program data t prog
KM29V040T, km29v040it flash memory 18 figure 6. block erase operation block erase the erase operation is done 4k bytes(1 block) at a time. block address loading is accomplished in two cycles initiated by an era se setup command(60h). only address a 12 to a 18 are valid while a 8 to a 11 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase, erase-verify and pulse repetition where required. 60h block add. : a 8 ~a 18 i/o 0 ~ 7 r/ b address input(2cycle) d0h read status the device contains a status register which may be read to find out whether program or erase operation is complete, and whether the program or erase operation completed successfully. after writing 70h command to the command register, a read cycle outputs the contents of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 2 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random r ead cycle, the required read command(00h) should be input before serial page read cycle. sr status definition i/o 0 program "0" : successful program "1" : error in program i/o 1 reserved for future use "0" i/o2 "0" i/o 3 "0" i/o 4 "0" i/o 5 "0" "0" i/o 6 device operation "0" : busy "1" : ready i/o 7 write protect "0" : protected "1" : not protected table2. status register definition t bers
KM29V040T, km29v040it flash memory 19 figure 7. reset operation ready/ busy the device has a r/ b output that provides a hardware method of indicating the completion of a frame program, erase or read seek completion. the r/ b pin is normally high but transitions to low after program or erase command is written to the command register or a random read is begin after address loading. it returns to high when the internal controller has finished the operation. the pi n is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. an appropriate pull-up resister is required for proper opera- tion and the value may be calculated by following equation. reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during the read, program or erase mode, the reset operation will abort these operation. in the case of reset during program or erase opera- tions, the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the d evice enters the read mode after completion of reset operation as shown table 3. if the device is already in reset state a new reset com- mand will not be accepted to by the command register. the r/ b pin transitions to low for t rst after the reset command is written. reset command is not necessarily for normal device operation. refer to figure 7 below. after power-up after reset operation mode read read ffh i/o 0 ~ 7 r/ b rp = v cc r/ b open drain output device gnd v cc (max.) - v ol (max.) i ol + s i l = note* 8ma + s i l where i l is the sum of the input currents of all devices tied to the r/ b pin. table3. device status note* km29n040 ; 5.1v km29v040 ; 3.2v t rst km29w040a ; 5.1v when vcc=3.6v~5.5v 3.2v when vcc=3.0v~3.6v
KM29V040T, km29v040it flash memory 20 figure 8. ac waveforms for power transition data protecttion the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage dete ctor disables all functions whenever vcc is below about 2v. wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down as shown in figure 8. the two step command sequence for program/erase provides additional software protection. v cc wp high figure 9. read id operation read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inpu t of 00h. two read cycles sequentially output the manufacture code(ech), and the device code (note*). the command register remains in read id mode until further commands are issued to it. figure 9 shows the operation sequence. ce cle i/o 0 ~ 7 ale re we 90h add. input(1cycle) dout(ech) dout( note* ) a 0 ~a 7 :"0" maker code device code t cr t whrid t ar t rea note* : km29v040 : a4h km29n040 : a4h km29w040 : a4h ? ?
KM29V040T, km29v040it flash memory 21 package dimensions unit :mm/inch 0~8 0 . 0 0 2 0.805 #1 44(40) lead plastic thin small out-line package type(ii) 0 . 0 5 #22(20) #44(40) #23(21) 0.032 0.35 0.10 0.014 0.004 0.80 0.0315 m i n . 0 . 0 4 7 1 . 2 0 m a x . 0.741 18.81 max. 18.41 0.10 0.725 0.004 +0.10 -0.05 +0.004 -0.002 0.15 0.006 1 0 . 1 6 0 . 4 0 0 44(40) - tsop2 - 400f 0.10 0.004 0.50 0.020 0.25 0.010 typ 0 . 4 5 ~ 0 . 7 5 0 . 0 1 8 ~ 0 . 0 3 0 0 . 0 3 9 0 . 0 0 4 1 . 0 0 0 . 1 0 max 1 1 . 7 6 0 . 2 0 0 . 4 6 3 0 . 0 0 8 ( )

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